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Example Designs
The example designs for the 2x QSFP28 FMC are hosted on Github.
| Example Designs | |||
|---|---|---|---|
| 100G/40G Ethernet Example Design | More info | Git repo | Docs |
| 100G Zircon IP Stack Example Design | More info | Git repo | Docs |
| IBERT Loopback Test Designs | More info | Git repo | Docs |
100G/40G Ethernet based example
Description
This example design demonstrates 100G and 40G Ethernet connectivity with QSFP28 modules on AMD Versal, Zynq UltraScale+ and Kintex UltraScale+ development boards. Each QSFP28 port carries a single Ethernet channel over its four bonded transceiver lanes, at a line rate set by the target board’s transceivers:
- 100G (CAUI-4) on the GTY-based boards, driven by a hardened 100G MAC: the AMD Xilinx Versal Integrated 100G Multirate Ethernet MAC (MRMAC) on the Versal VCK190, or the UltraScale+ Integrated 100G Ethernet (CMAC) on the RFSoC boards (ZCU111/ZCU208/ZCU216) and the Kintex UltraScale+ KCU116.
- 40G (40GBASE-R4) on the GTH-based ZCU102 and ZCU106, driven by the soft 40G/50G Ethernet Subsystem MAC/PCS, which is also available as alternative targets of the GTY boards.
In every design, packet data is moved to and from DDR by an AXI MCDMA and the ports are driven under Linux (PetaLinux or Yocto) by the AXI Ethernet driver, or bare-metal by the included echo-server application. The KCU116 has no processing system, so it gets a MicroBlaze soft processor in front of the same datapath and is supported with the standalone application only.
Links
Block diagrams
Versal designs (100G MRMAC)
Zynq UltraScale+ designs (40G on GTH boards, 100G CMAC on RFSoC boards)
Kintex UltraScale+ KCU116 design (MicroBlaze, 100G CMAC)
Supported carrier boards
- AMD Xilinx KCU116 Kintex UltraScale+ Development board (standalone only, one port)
- AMD Xilinx ZCU102 Zynq UltraScale+ Development board (40G)
- AMD Xilinx ZCU106 Zynq UltraScale+ Development board (40G)
- AMD Xilinx ZCU111 Zynq UltraScale+ Development board
- AMD Xilinx ZCU208 Zynq UltraScale+ Development board
- AMD Xilinx ZCU216 Zynq UltraScale+ Development board
- AMD Xilinx VCK190 Versal AI Core Development board
100G Zircon IP stack example
Description
This example design puts the open-source Zircon IP stack from the FPGA Ninja Taxi transport library behind each of the two 100G Ethernet ports. On the Versal VCK190, each port is driven by its own Integrated MRMAC (CAUI-4, RS-FEC) and Zircon parses and builds the Ethernet/IPv4/UDP headers in hardware, so there is no processor in the datapath. Each port provides a hardware UDP echo, a hardware UDP socket to the processing system, a raw control-plane path (lwIP, for ARP/ICMP/DHCP/TCP), a hardware UDP traffic generator and checker, rate meters and hardware latency measurement using the MRMAC’s IEEE 1588 timestamps. The design sustains full 100 Gb/s line rate in both directions with UDP payloads of 726 bytes and up.
A second target, the Kintex UltraScale+ KCU116, runs the same Zircon datapath on one port using the device’s integrated 100G CMAC with a MicroBlaze control plane. It builds with the free Vivado Standard edition.
Links
Block diagram
Supported carrier boards
- AMD Xilinx VCK190 Versal AI Core Development board (both ports)
- AMD Xilinx KCU116 Kintex UltraScale+ Development board (one port, MicroBlaze)
IBERT loopback test designs
Description
These projects test the 2x QSFP28 FMC in loopback using the AMD IBERT (Integrated Bit Error Ratio Tester) core, with either active or passive loopback modules in the QSFP28 cages. They let you run eye scans and measure the link quality of all eight lanes at 10G and 28G line rates. We use these projects internally for development and production test, but feel free to use them to build your own similar test setups. The same repository also contains IBERT designs for our other transceiver-based FMCs.