Programming Guide

This section provides the details of the programming requirements to operate the 2x QSFP28 FMC hardware and customise functionality.

QSFP I/Os

The QSFP28 management I/O signals must be driven by the FPGA to appropriate levels in order to configure the QSFP/QSFP+/QSFP28 modules for normal operation.

Module Reset

The QSFP28 module input RESET_L allows the FPGA to reset the module. In normal operation, this input should be driven HIGH to allow the module to operate normally. A LOW pulse can be used to reset the module.

NetDescriptionFMC pinValue for normal operation
QSFP0_RESETL_TPort 0: Module reset (active low)LA04_NHIGH (1)
QSFP1_RESETL_TPort 1: Module reset (active low)LA15_NHIGH (1)

Low Power Mode

The QSFP28 module input LPMODE allows the FPGA to set the module to low power mode. In normal operation, this input should be driven LOW to allow the module to operate at full power.

NetDescriptionFMC pinValue for normal operation
QSFP0_LPMODE_TPort 0: Low Power ModeLA11_PLOW (0)
QSFP1_LPMODE_TPort 1: Low Power ModeLA11_NLOW (0)

Module Select

The QSFP28 module input MODSEL_L selects the module for I2C communication. When driven LOW, the module responds to I2C transactions on its bus. In normal operation, this should be driven LOW to enable I2C communication.

NetDescriptionFMC pinValue for normal operation
QSFP0_MODSELL_TPort 0: Module Select (active low)LA04_PLOW (0)
QSFP1_MODSELL_TPort 1: Module Select (active low)LA15_PLOW (0)

Clock multiplier

The jitter-attenuating clock multiplier ( Skyworks, Si5328 ) must be configured via the PL I2C bus to enable appropriate clocks for the QSFP/QSFP+/QSFP28 modules used.

The CLK I2C bus signals are connected to the FMC pins listed in the table below:

Net NameDescriptionFMC pin
CLK_I2C_SCL_TI2C clock (SCL)LA02_P
CLK_I2C_SDA_TI2C data (SDA)LA02_N

The Si5328 has the I2C address 0x68.

A6A5A4A3A2A1A0Hexadecimal
11010000x68

Refer to the Si5328 datasheet for detailed information on the device registers and how to configure the clock outputs.

QSFP I2C

Note that the I2C addresses of the QSFP/QSFP+/QSFP28 modules are dependent on the specific module used. Refer to the module datasheet for this information. Remember to assert MODSEL_L (drive LOW) before attempting I2C communication with a QSFP28 module.

EEPROM

The 2K EEPROM is intended to store information that identifies the mezzanine card and also specifies the power supplies required by the card. This information is typically read by the system power management on the carrier board when it is powered up. In typical user applications, it should not be necessary to read the data on the EEPROM, and we highly recommend against writing to the EEPROM. Nevertheless, if you wish to access the EEPROM, it can be read and written to at the I2C address 0x50.

A6A5A4A3A2A1A0Hexadecimal
10100000x50

The EEPROM sits on the FMC card’s dedicated I2C bus. The FMC pins of the EEPROM’s I2C bus are shown below, and it is up to the user to determine their corresponding connections to the FPGA/MPSoC on the carrier board being used.

I2C bus signalFMC pin nameFMC pin number
SCL (clock)SCLC30
SDA (data)SDAC31

Restoring contents

If you need to reprogram the EEPROM with the original factory contents, you can use the Opsero FMC EEPROM Tool.