Datasheet on Opsero Docshttps://docs.opsero.com/op120/datasheet/Recent content in Datasheet on Opsero DocsHugoenCopyright (c) 2026 Opsero Electronic Design Inc.Tue, 24 Feb 2026 00:00:00 -0500Overviewhttps://docs.opsero.com/op120/datasheet/overview/Tue, 24 Feb 2026 00:00:00 -0500https://docs.opsero.com/op120/datasheet/overview/<h2 id="description">Description</h2> <p>The 2x QSFP28 FMC is an add-on expansion board (FPGA Mezzanine Card) for FPGA and SoC-based development boards. It has two QSFP28 module slots, allowing the connection of up to two QSFP28, QSFP+ or QSFP modules to the carrier development board. Each QSFP28 port provides four lanes of up to 25 Gbps each, for an aggregate bandwidth of up to 100 Gbps per port. The mezzanine card features a jitter-attenuating clock multiplier, supporting Synchronous Ethernet applications, and uses level translators to support a wide range of FPGA I/O voltages from 1.2VDC to 3.3VDC.</p>Pin Configurationhttps://docs.opsero.com/op120/datasheet/pin-configuration/Tue, 24 Feb 2026 00:00:00 -0500https://docs.opsero.com/op120/datasheet/pin-configuration/<h2 id="pinout-table">Pinout table</h2> <p>The 2x QSFP28 FMC has a high pin count FPGA Mezzanine Card (FMC) connector, providing the connections to the FPGA on the development board. The following table defines the pinout of the FMC connector and describes each pin&rsquo;s purpose on this mezzanine card.</p>Specificationshttps://docs.opsero.com/op120/datasheet/specifications/Tue, 24 Feb 2026 00:00:00 -0500https://docs.opsero.com/op120/datasheet/specifications/<h2 id="recommended-operating-conditions">Recommended Operating Conditions</h2> <table> <thead> <tr> <th>SUPPLY VOLTAGE</th> <th>MIN</th> <th>TYP</th> <th>MAX</th> <th>UNIT</th> </tr> </thead> <tbody> <tr> <td>12 VDC</td> <td>+11.4</td> <td>+12</td> <td>+12.6</td> <td>V</td> </tr> <tr> <td>3.3 VDC</td> <td>+3.14</td> <td>+3.3</td> <td>+3.46</td> <td>V</td> </tr> <tr> <td>VADJ (1.2VDC)</td> <td>+1.14</td> <td>+1.2</td> <td>+1.26</td> <td>V</td> </tr> <tr> <td>VADJ (1.5VDC)</td> <td>+1.425</td> <td>+1.5</td> <td>+1.575</td> <td>V</td> </tr> <tr> <td>VADJ (1.8VDC)</td> <td>+1.71</td> <td>+1.8</td> <td>+1.89</td> <td>V</td> </tr> <tr> <td>VADJ (2.5VDC)</td> <td>+2.375</td> <td>+2.5</td> <td>+2.625</td> <td>V</td> </tr> <tr> <td>VADJ (3.3VDC)</td> <td>+3.135</td> <td>+3.3</td> <td>+3.465</td> <td>V</td> </tr> </tbody> </table> <p>Notes:</p>Detailed Descriptionhttps://docs.opsero.com/op120/datasheet/detailed-description/Tue, 24 Feb 2026 00:00:00 -0500https://docs.opsero.com/op120/datasheet/detailed-description/<h2 id="hardware-overview">Hardware Overview</h2> <p>The figure below illustrates the various hardware components that are located on the top-side (component side) of the 2x QSFP28 FMC.</p>Mechanical Informationhttps://docs.opsero.com/op120/datasheet/mechanical/Tue, 24 Feb 2026 00:00:00 -0500https://docs.opsero.com/op120/datasheet/mechanical/<h2 id="height-profile">Height Profile</h2> <p>The figure below illustrates the height profile of the 2x QSFP28 FMC.</p> <p> <img src="https://docs.opsero.com/images/op120-2x-qsfp28-fmc/op120-2x-qsfp28-fmc-sideortho_hu_db493056e088c64e.webp" width="1080" height="400" decoding="async" fetchpriority="auto" loading="lazy" alt="2x QSFP28 FMC profile"title="2x QSFP28 FMC profile" id="h-rh-i-0" ></p>Compatible Boardshttps://docs.opsero.com/op120/datasheet/compatibility/Tue, 24 Feb 2026 00:00:00 -0500https://docs.opsero.com/op120/datasheet/compatibility/<p>This section of the documentation aims to list all of the development boards for which compatibility with the 2x QSFP28 FMC has been checked, and to list constraints and any notes concerning special requirements or limitations with the board.</p>Board Revision Historyhttps://docs.opsero.com/op120/datasheet/revision/Tue, 24 Feb 2026 00:00:00 -0500https://docs.opsero.com/op120/datasheet/revision/<h2 id="rev-a">Rev A</h2> <ul> <li>First boards manufactured</li> </ul> <h2 id="rev-b">Rev B</h2> <ul> <li>First commercial release</li> <li>Rev B was designed to improve the signal integrity of the first revision and improve yield</li> <li>Copper layers increased to 12 (from 8)</li> <li>I2C voltage translators changed to TCA9416DDFR to improve manufacturing yield</li> </ul>