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Compatible Boards
This section of the documentation aims to list all of the development boards for which compatibility with the 2x QSFP28 FMC has been checked, and to list constraints and any notes concerning special requirements or limitations with the board.
The 2x QSFP28 FMC requires 8 gigabit transceivers (DP0-DP7) to support both QSFP28 ports.
Low pin count (LPC) FMC connectors only provide a single transceiver (DP0) and therefore
cannot support any QSFP28 port on this mezzanine card. A high pin count (HPC) or FMC+ connector
with at least DP0-DP3 routed is required to use Port 0 (1 port), and DP0-DP7 routed is required
to use both ports.
List of boards
The following development boards have been verified compatible with the 2x QSFP28 FMC. For more detailed information regarding compatibility with a particular development board, including the availability of an example design, click on the name of the board in the table below.
Zynq Ultrascale+ boards
| Carrier | FMC | Compatible | Ref design | Supported Ports | Supported Link Speed |
|---|---|---|---|---|---|
| AMD Xilinx ZCU102 Zynq UltraScale+ Development board | HPC0 | ✅ | Coming soon | 2 | 2x 40G |
| AMD Xilinx ZCU102 Zynq UltraScale+ Development board | HPC1 | ✅ | Coming soon | 2 | 2x 40G |
| AMD Xilinx ZCU106 Zynq UltraScale+ Development board | HPC0 | ✅ | Coming soon | 2 | 2x 40G |
| AMD Xilinx ZCU111 Zynq UltraScale+ Development board | FMC+ | ✅ | Coming soon | 2 | 2x 100G |
| AMD Xilinx ZCU208 Zynq UltraScale+ Development board | FMC+ | ✅ | Coming soon | 2 | 2x 100G |
| AMD Xilinx ZCU216 Zynq UltraScale+ Development board | FMC+ | ✅ | Coming soon | 2 | 2x 100G |
| Avnet UltraZed EV Carrier Zynq UltraScale+ Development board | HPC | ✅ | Coming soon | 2 | 2x 40G |
Ultrascale+ boards
| Carrier | FMC | Compatible | Ref design | Supported Ports | Supported Link Speed |
|---|---|---|---|---|---|
| AMD Xilinx VCU118 Virtex UltraScale+ Development board | FMC+ | ✅ | Coming soon | 2 | 2x 40G |
Versal boards
| Carrier | FMC | Compatible | Ref design | Supported Ports | Supported Link Speed |
|---|---|---|---|---|---|
| AMD Xilinx VCK190 Versal AI Core Development board | FMC+1 | ✅ | Coming soon | 2 | 2x 100G |
| AMD Xilinx VCK190 Versal AI Core Development board | FMC+2 | ✅ | Coming soon | 2 | 2x 100G |
| AMD Xilinx VEK280 Versal AI Edge Development board | FMC+ | ✅ | Coming soon | 2 | 2x 100G |
| AMD Xilinx VHK158 Versal HBM Series Development board | FMC+ | ✅ | Coming soon | 2 | 2x 100G |
| AMD Xilinx VMK180 Versal Prime Series Development board | FMC+1 | ✅ | Coming soon | 2 | 2x 100G |
| AMD Xilinx VMK180 Versal Prime Series Development board | FMC+2 | ✅ | Coming soon | 2 | 2x 100G |
| AMD Xilinx VPK120 Versal Premium Series Development board | FMC+ | ✅ | Coming soon | 2 | 2x 100G |
| AMD Xilinx VPK180 Versal Premium Series Development board | FMC+ | ✅ | Coming soon | 2 | 2x 100G |
Compatibility requirements
If you need to determine the compatibility of a development board that is not listed here, or you are designing a carrier board to mate with the 2x QSFP28 FMC, please check your board against the list of requirements below.
VADJ
The development board must have the ability to supply a VADJ voltage between 1.2VDC and 3.3VDC. The 2x QSFP28 FMC has an EEPROM containing IPMI data to be used by a power management device. If the development board has such a power management device, an appropriate VADJ voltage will be applied automatically on power-up. Note that some development boards require the VADJ voltage to be configured by a DIP switch or jumper placement.
Gigabit transceivers
The FPGA or MPSoC device must have gigabit transceivers and they must be routed to the FMC connector. Each QSFP28 port requires four gigabit transceivers. Port 0 uses DP0-DP3 and Port 1 uses DP4-DP7. All eight transceivers must be connected to the FPGA for both QSFP28 ports to work.
| Port | Lane | Signal direction | FMC Pin | FMC pin name |
|---|---|---|---|---|
| 0 | 0 | Link partner to FPGA | C6/C7 | DP0_M2C_P/N |
| FPGA to Link partner | C2/C3 | DP0_C2M_P/N | ||
| 0 | 1 | Link partner to FPGA | A2/A3 | DP1_M2C_P/N |
| FPGA to Link partner | A22/A23 | DP1_C2M_P/N | ||
| 0 | 2 | Link partner to FPGA | A6/A7 | DP2_M2C_P/N |
| FPGA to Link partner | A26/A27 | DP2_C2M_P/N | ||
| 0 | 3 | Link partner to FPGA | A10/A11 | DP3_M2C_P/N |
| FPGA to Link partner | A30/A31 | DP3_C2M_P/N | ||
| 1 | 0 | Link partner to FPGA | A14/A15 | DP4_M2C_P/N |
| FPGA to Link partner | A34/A35 | DP4_C2M_P/N | ||
| 1 | 1 | Link partner to FPGA | A18/A19 | DP5_M2C_P/N |
| FPGA to Link partner | A38/A39 | DP5_C2M_P/N | ||
| 1 | 2 | Link partner to FPGA | B16/B17 | DP6_M2C_P/N |
| FPGA to Link partner | B36/B37 | DP6_C2M_P/N | ||
| 1 | 3 | Link partner to FPGA | B12/B13 | DP7_M2C_P/N |
| FPGA to Link partner | B32/B33 | DP7_C2M_P/N |
Note that low pin count (LPC) FMC connectors only have one possible GT connection (DP0). Since each QSFP28 port requires four GT lanes, LPC FMC connectors are not compatible with the 2x QSFP28 FMC.
At least one of the GT clock references (FMC pins GBTCLK0_M2C_P/N and GBTCLK1_M2C_P/N) should be connected to one of the GT reference clock inputs of the quad to which DP0-7 connect, or an adjacent quad.
Required I/O
The following FMC pins must be connected to the FPGA as they provide critical I/O to the mezzanine card.
| FMC Pin | FMC name | Net | Description |
|---|---|---|---|
| H7 | LA02_P | CLK_I2C_SCL_T | Clock multiplier I2C bus clock SCL |
| H8 | LA02_N | CLK_I2C_SDA_T | Clock multiplier I2C bus data SDA |
| G9 | LA03_P | QSFP0_I2C_SCL_T | Port 0: I2C Clock |
| G10 | LA03_N | QSFP0_I2C_SDA_T | Port 0: I2C Data (bidirectional) |
| D20 | LA17_P_CC | QSFP1_I2C_SCL_T | Port 1: I2C Clock |
| D21 | LA17_N_CC | QSFP1_I2C_SDA_T | Port 1: I2C Data (bidirectional) |
| H10 | LA04_P | QSFP0_MODSELL_T | Port 0: Module Select (active low) |
| H11 | LA04_N | QSFP0_RESETL_T | Port 0: Reset (active low) |
| H19 | LA15_P | QSFP1_MODSELL_T | Port 1: Module Select (active low) |
| H20 | LA15_N | QSFP1_RESETL_T | Port 1: Reset (active low) |
Featured I/O
The following FMC pins should ideally be connected to the FPGA as they provide extra functionality to the mezzanine card. These pins are not critical to the operation of the mezzanine card; it can operate without them if they are not connected on the carrier board.
| FMC Pin | FMC name | Net | Description |
|---|---|---|---|
| G15 | LA12_P | QSFP0_MODPRSL_T | Port 0: Module Present (active low) |
| G16 | LA12_N | QSFP0_INTL_T | Port 0: Interrupt (active low) |
| D11 | LA05_P | QSFP1_MODPRSL_T | Port 1: Module Present (active low) |
| D12 | LA05_N | QSFP1_INTL_T | Port 1: Interrupt (active low) |
| H16 | LA11_P | QSFP0_LPMODE_T | Port 0: Low Power Mode |
| H17 | LA11_N | QSFP1_LPMODE_T | Port 1: Low Power Mode |
| G12 | LA08_P | QSFP1_GRN_LED_T | Port 1: User bicolor LED Green |
| G13 | LA08_N | QSFP1_RED_LED_T | Port 1: User bicolor LED Red |
| H13 | LA07_P | QSFP0_GRN_LED_T | Port 0: User bicolor LED Green |
| H14 | LA07_N | QSFP0_RED_LED_T | Port 0: User bicolor LED Red |
| G6 | LA00_P_CC | REC_CLK1_P | Recovered clock positive (LVDS, FPGA to Si5328) |
| G7 | LA00_N_CC | REC_CLK1_N | Recovered clock negative (LVDS, FPGA to Si5328) |
| C10 | LA06_P | CLK_LOS_ALARM_T | Clock loss alarm from Si5328 |