Pin Configuration

Pinout table

The MCIO PCIe FMC has a high pin count FPGA Mezzanine Card (FMC) connector, providing the connections to the FPGA on the development board. The following table defines the pinout of the FMC connector and describes each pin’s purpose on this mezzanine card.

The PCIe nets have been labelled as follows:

PERA: PCIe RX for MCIO Channel A
PETA: PCIe TX for MCIO Channel A
PERB: PCIe RX for MCIO Channel B
PETB: PCIe TX for MCIO Channel B

Note that although the 8xMCIO connector is divided into two channels A and B, it can also be used as a single 8-lane PCIe connection.

Pin	Pin name	Net	Description
A1	GND	GND	Ground
A2	DP1_M2C_P	PERA_1_P	PCIe lane 1 positive (MCIOA-to-FPGA)
A3	DP1_M2C_N	PERA_1_N	PCIe lane 1 negative (MCIOA-to-FPGA)
A4	GND	GND	Ground
A5	GND	GND	Ground
A6	DP2_M2C_P	PERA_2_P	PCIe lane 2 positive (MCIOA-to-FPGA)
A7	DP2_M2C_N	PERA_2_N	PCIe lane 2 negative (MCIOA-to-FPGA)
A8	GND	GND	Ground
A9	GND	GND	Ground
A10	DP3_M2C_P	PERA_3_P	PCIe lane 3 positive (MCIOA-to-FPGA)
A11	DP3_M2C_N	PERA_3_N	PCIe lane 3 negative (MCIOA-to-FPGA)
A12	GND	GND	Ground
A13	GND	GND	Ground
A14	DP4_M2C_P	PERB_0_P	PCIe lane 0 positive (MCIOB-to-FPGA)
A15	DP4_M2C_N	PERB_0_N	PCIe lane 0 negative (MCIOB-to-FPGA)
A16	GND	GND	Ground
A17	GND	GND	Ground
A18	DP5_M2C_P	PERB_1_P	PCIe lane 1 positive (MCIOB-to-FPGA)
A19	DP5_M2C_N	PERB_1_N	PCIe lane 1 negative (MCIOB-to-FPGA)
A20	GND	GND	Ground
A21	GND	GND	Ground
A22	DP1_C2M_P	PETA_1_P	PCIe lane 1 positive (FPGA-to-MCIOA)
A23	DP1_C2M_N	PETA_1_N	PCIe lane 1 negative (FPGA-to-MCIOA)
A24	GND	GND	Ground
A25	GND	GND	Ground
A26	DP2_C2M_P	PETA_2_P	PCIe lane 2 positive (FPGA-to-MCIOA)
A27	DP2_C2M_N	PETA_2_N	PCIe lane 2 negative (FPGA-to-MCIOA)
A28	GND	GND	Ground
A29	GND	GND	Ground
A30	DP3_C2M_P	PETA_3_P	PCIe lane 3 positive (FPGA-to-MCIOA)
A31	DP3_C2M_N	PETA_3_N	PCIe lane 3 negative (FPGA-to-MCIOA)
A32	GND	GND	Ground
A33	GND	GND	Ground
A34	DP4_C2M_P	PETB_0_P	PCIe lane 0 positive (FPGA-to-MCIOB)
A35	DP4_C2M_N	PETB_0_N	PCIe lane 0 negative (FPGA-to-MCIOB)
A36	GND	GND	Ground
A37	GND	GND	Ground
A38	DP5_C2M_P	PETB_1_P	PCIe lane 1 positive (FPGA-to-MCIOB)
A39	DP5_C2M_N	PETB_1_N	PCIe lane 1 negative (FPGA-to-MCIOB)
A40	GND	GND	Ground
B1	CLK_DIR	N/C	Not connected
B2	GND	GND	Ground
B3	GND	GND	Ground
B4	DP9_M2C_P	N/C	Not connected
B5	DP9_M2C_N	N/C	Not connected
B6	GND	GND	Ground
B7	GND	GND	Ground
B8	DP8_M2C_P	N/C	Not connected
B9	DP8_M2C_N	N/C	Not connected
B10	GND	GND	Ground
B11	GND	GND	Ground
B12	DP7_M2C_P	PERB_3_P	PCIe lane 3 positive (MCIOB-to-FPGA)
B13	DP7_M2C_N	PERB_3_N	PCIe lane 3 negative (MCIOB-to-FPGA)
B14	GND	GND	Ground
B15	GND	GND	Ground
B16	DP6_M2C_P	PERB_2_P	PCIe lane 2 positive (MCIOB-to-FPGA)
B17	DP6_M2C_N	PERB_2_N	PCIe lane 2 negative (MCIOB-to-FPGA)
B18	GND	GND	Ground
B19	GND	GND	Ground
B20	GBTCLK1_M2C_P	CLKB_F_P	100MHz PCIe reference clock for the FPGA
B21	GBTCLK1_M2C_N	CLKB_F_N	100MHz PCIe reference clock for the FPGA
B22	GND	GND	Ground
B23	GND	GND	Ground
B24	DP9_C2M_P	N/C	Not connected
B25	DP9_C2M_N	N/C	Not connected
B26	GND	GND	Ground
B27	GND	GND	Ground
B28	DP8_C2M_P	N/C	Not connected
B29	DP8_C2M_N	N/C	Not connected
B30	GND	GND	Ground
B31	GND	GND	Ground
B32	DP7_C2M_P	PETB_3_P	PCIe lane 3 positive (FPGA-to-MCIOB)
B33	DP7_C2M_N	PETB_3_N	PCIe lane 3 negative (FPGA-to-MCIOB)
B34	GND	GND	Ground
B35	GND	GND	Ground
B36	DP6_C2M_P	PETB_2_P	PCIe lane 2 positive (FPGA-to-MCIOB)
B37	DP6_C2M_N	PETB_2_N	PCIe lane 2 negative (FPGA-to-MCIOB)
B38	GND	GND	Ground
B39	GND	GND	Ground
B40	RES0	N/C	Not connected
C1	GND	GND	Ground
C2	DP0_C2M_P	PETA_0_P	PCIe lane 0 positive (FPGA-to-MCIOA)
C3	DP0_C2M_N	PETA_0_N	PCIe lane 0 negative (FPGA-to-MCIOA)
C4	GND	GND	Ground
C5	GND	GND	Ground
C6	DP0_M2C_P	PERA_0_P	PCIe lane 0 positive (MCIOA-to-FPGA)
C7	DP0_M2C_N	PERA_0_N	PCIe lane 0 negative (MCIOA-to-FPGA)
C8	GND	GND	Ground
C9	GND	GND	Ground
C10	LA06_P	N/C	Not connected
C11	LA06_N	N/C	Not connected
C12	GND	GND	Ground
C13	GND	GND	Ground
C14	LA10_P	SBA_DISABLE_T	Disable sideband A signals
C15	LA10_N	SBB_DISABLE_T	Disable sideband B signals
C16	GND	GND	Ground
C17	GND	GND	Ground
C18	LA14_P	HOST_MODE_N_T	Host mode enable active-low (0:HOST MODE, 1:DEVICE MODE)
C19	LA14_N	LOCAL_CLKS_N_T	Local/remote clock select (0:LOCAL, 1:REMOTE)
C20	GND	GND	Ground
C21	GND	GND	Ground
C22	LA18_P_CC	N/C	Not connected
C23	LA18_N_CC	N/C	Not connected
C24	GND	GND	Ground
C25	GND	GND	Ground
C26	LA27_P	N/C	Not connected
C27	LA27_N	N/C	Not connected
C28	GND	GND	Ground
C29	GND	GND	Ground
C30	SCL	I2C_SCL	I2C Clock (FPGA-to-PHY)
C31	SDA	I2C_SDA	I2C Data (bidirectional)
C32	GND	GND	Ground
C33	GND	GND	Ground
C34	GA0	GA0	EEPROM Address Bit 1 (A1)
C35	12P0V_1	12V0	12VDC
C36	GND	GND	Ground
C37	12P0V_2	12V0	12VDC
C38	GND	GND	Ground
C39	3P3V_1	3V3	3.3VDC
C40	GND	GND	Ground
D1	PG_C2M	PG	Power Good (Driven by carrier)
D2	GND	GND	Ground
D3	GND	GND	Ground
D4	GBTCLK0_M2C_P	CLKA_F_P	100MHz PCIe reference clock for the FPGA
D5	GBTCLK0_M2C_N	CLKA_F_N	100MHz PCIe reference clock for the FPGA
D6	GND	GND	Ground
D7	GND	GND	Ground
D8	LA01_P_CC	N/C	Not connected
D9	LA01_N_CC	N/C	Not connected
D10	GND	GND	Ground
D11	LA05_P	N/C	Not connected
D12	LA05_N	N/C	Not connected
D13	GND	GND	Ground
D14	LA09_P	N/C	Not connected
D15	LA09_N	N/C	Not connected
D16	GND	GND	Ground
D17	LA13_P	N/C	Not connected
D18	LA13_N	N/C	Not connected
D19	GND	GND	Ground
D20	LA17_P_CC	N/C	Not connected
D21	LA17_N_CC	N/C	Not connected
D22	GND	GND	Ground
D23	LA23_P	N/C	Not connected
D24	LA23_N	N/C	Not connected
D25	GND	GND	Ground
D26	LA26_P	N/C	Not connected
D27	LA26_N	N/C	Not connected
D28	GND	GND	Ground
D29	TCK	N/C	Not used
D30	TDI	TDI-TDO	JTAG TDI (Connects to TDO to close JTAG chain)
D31	TDO	TDI-TDO	JTAG TDO (Connects to TDI to close JTAG chain)
D32	3P3VAUX	3V3AUX	3.3VDC Power supply for EEPROM
D33	TMS	N/C	Not used
D34	TRST_L	N/C	Not used
D35	GA1	GA1	EEPROM Address Bit 0 (A0)
D36	3P3V_2	3V3	3.3VDC
D37	GND	GND	Ground
D38	3P3V_3	3V3	3.3VDC
D39	GND	GND	Ground
D40	3P3V_4	3V3	3.3VDC
G1	GND	GND	Ground
G2	CLK1_M2C_P	N/C	Not used
G3	CLK1_M2C_N	N/C	Not used
G4	GND	GND	Ground
G5	GND	GND	Ground
G6	LA00_P_CC	PERSTA_N_T	PCIe reset for MCIOA (active LOW)
G7	LA00_N_CC	CPRSNTA_N_T	PCIe detect for MCIOA
G8	GND	GND	Ground
G9	LA03_P	N/C	Not connected
G10	LA03_N	N/C	Not connected
G11	GND	GND	Ground
G12	LA08_P	N/C	Not connected
G13	LA08_N	N/C	Not connected
G14	GND	GND	Ground
G15	LA12_P	MCIOA_I2C_SCL	I2C clock for MCIO Channel A
G16	LA12_N	MCIOA_I2C_SDA	I2C data for MCIO Channel A
G17	GND	GND	Ground
G18	LA16_P	N/C	Not connected
G19	LA16_N	N/C	Not connected
G20	GND	GND	Ground
G21	LA20_P	N/C	Not connected
G22	LA20_N	N/C	Not connected
G23	GND	GND	Ground
G24	LA22_P	N/C	Not connected
G25	LA22_N	N/C	Not connected
G26	GND	GND	Ground
G27	LA25_P	N/C	Not connected
G28	LA25_N	N/C	Not connected
G29	GND	GND	Ground
G30	LA29_P	N/C	Not connected
G31	LA29_N	N/C	Not connected
G32	GND	GND	Ground
G33	LA31_P	N/C	Not connected
G34	LA31_N	N/C	Not connected
G35	GND	GND	Ground
G36	LA33_P	N/C	Not connected
G37	LA33_N	N/C	Not connected
G38	GND	GND	Ground
G39	VADJ_3	VADJ	I/O Supply Voltage
G40	GND	GND	Ground
H1	VREF_A_M2C	N/C	Not used
H2	PRSNT_M2C_L	GND	Ground
H3	GND	GND	Ground
H4	CLK0_M2C_P	N/C	Not used
H5	CLK0_M2C_N	N/C	Not used
H6	GND	GND	Ground
H7	LA02_P	N/C	Not connected
H8	LA02_N	N/C	Not connected
H9	GND	GND	Ground
H10	LA04_P	PERSTA_N_T	PCIe reset for MCIOB (active LOW)
H11	LA04_N	CPRSNTA_N_T	PCIe detect for MCIOB
H12	GND	GND	Ground
H13	LA07_P	N/C	Not used
H14	LA07_N	N/C	Not used
H15	GND	GND	Ground
H16	LA11_P	MCIOB_I2C_SCL	I2C clock for MCIO Channel B
H17	LA11_N	MCIOB_I2C_SDA	I2C data for MCIO Channel B
H18	GND	GND	Ground
H19	LA15_P	RDRV_I2C_SCL	I2C clock for Redrivers
H20	LA15_N	RDRV_I2C_SDA	I2C data for Redrivers
H21	GND	GND	Ground
H22	LA19_P	N/C	Not connected
H23	LA19_N	N/C	Not connected
H24	GND	GND	Ground
H25	LA21_P	N/C	Not connected
H26	LA21_N	N/C	Not connected
H27	GND	GND	Ground
H28	LA24_P	N/C	Not connected
H29	LA24_N	N/C	Not connected
H30	GND	GND	Ground
H31	LA28_P	N/C	Not connected
H32	LA28_N	N/C	Not connected
H33	GND	GND	Ground
H34	LA30_P	N/C	Not connected
H35	LA30_N	N/C	Not connected
H36	GND	GND	Ground
H37	LA32_P	N/C	Not connected
H38	LA32_N	N/C	Not connected
H39	GND	GND	Ground
H40	VADJ_4	VADJ	I/O Supply Voltage

Rows E,F,J and K of the HPC connector were left out of the above table. On the mezzanine card, these rows are left unconnected, with the exception of the ground and VADJ pins which are connected appropriately.

MCIO PCIe FMC (OP103)

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Pin Configuration

Pinout table

Pin Configuration

Pinout table#

Pinout table