Datasheet on Opsero Docshttps://docs.opsero.com/op103/datasheet/Recent content in Datasheet on Opsero DocsHugoenCopyright (c) 2026 Opsero Electronic Design Inc.Wed, 11 Feb 2026 08:13:00 -0500Overviewhttps://docs.opsero.com/op103/datasheet/overview/Wed, 11 Feb 2026 08:00:40 -0500https://docs.opsero.com/op103/datasheet/overview/<h2 id="description">Description</h2> <p>The MCIO PCIe FMC is an FPGA Mezzanine Card designed to bring high-speed MCIO PCIe connectivity to FPGA and MPSoC development boards. It connects to the development board via a high pin count (HPC) FMC connector and provides an 8-lane MCIO PCIe connector with all 8 lanes routed to gigabit transceivers on the FMC interface. The card supports PCIe Gen4 speeds (16 GT/s per lane) and incorporates two TI PCIe redrivers ( TI, 8-lane PCIe Gen4 Redriver, <a href=https://download.opsero.com/datasheet/ds320pr810.pdf target="_blank">DS320PR810</a> ) to compensate for signal loss across MCIO cables and adapters.</p>Pin Configurationhttps://docs.opsero.com/op103/datasheet/pin-configuration/Wed, 11 Feb 2026 08:11:11 -0500https://docs.opsero.com/op103/datasheet/pin-configuration/<h2 id="pinout-table">Pinout table</h2> <p>The MCIO PCIe FMC has a high pin count FPGA Mezzanine Card (FMC) connector, providing the connections to the FPGA on the development board. The following table defines the pinout of the FMC connector and describes each pin&rsquo;s purpose on this mezzanine card.</p>Specificationshttps://docs.opsero.com/op103/datasheet/specifications/Wed, 11 Feb 2026 08:11:27 -0500https://docs.opsero.com/op103/datasheet/specifications/<h2 id="recommended-operating-conditions">Recommended Operating Conditions</h2> <table> <thead> <tr> <th>SUPPLY VOLTAGE</th> <th>MIN</th> <th>TYP</th> <th>MAX</th> <th>UNIT</th> </tr> </thead> <tbody> <tr> <td>12 VDC</td> <td>+11.4</td> <td>+12</td> <td>+12.6</td> <td>V</td> </tr> <tr> <td>3.3 VDC</td> <td>+3.14</td> <td>+3.3</td> <td>+3.46</td> <td>V</td> </tr> <tr> <td>VADJ (1.2VDC)</td> <td>+1.14</td> <td>+1.2</td> <td>+1.26</td> <td>V</td> </tr> <tr> <td>VADJ (1.5VDC)</td> <td>+1.425</td> <td>+1.5</td> <td>+1.575</td> <td>V</td> </tr> <tr> <td>VADJ (1.8VDC)</td> <td>+1.71</td> <td>+1.8</td> <td>+1.89</td> <td>V</td> </tr> <tr> <td>VADJ (2.5VDC)</td> <td>+2.375</td> <td>+2.5</td> <td>+2.625</td> <td>V</td> </tr> <tr> <td>VADJ (3.3VDC)</td> <td>+3.135</td> <td>+3.3</td> <td>+3.465</td> <td>V</td> </tr> </tbody> </table> <p>Notes:</p>Detailed Descriptionhttps://docs.opsero.com/op103/datasheet/detailed-description/Wed, 11 Feb 2026 08:11:40 -0500https://docs.opsero.com/op103/datasheet/detailed-description/<h2 id="hardware-overview">Hardware Overview</h2> <p>The figure below illustrates the various hardware components that are located on the top-side of the MCIO PCIe FMC.</p>Mechanical Informationhttps://docs.opsero.com/op103/datasheet/mechanical/Wed, 11 Feb 2026 08:11:54 -0500https://docs.opsero.com/op103/datasheet/mechanical/<h2 id="dimensions">Dimensions</h2> <p>The mechanical dimensions of the MCIO PCIe FMC are illustrated in the figures below. All dimensions are in millimeters (mm).</p>Compatible Boardshttps://docs.opsero.com/op103/datasheet/compatibility/Wed, 11 Feb 2026 08:12:15 -0500https://docs.opsero.com/op103/datasheet/compatibility/<p>The following development boards are compatible with the MCIO PCIe FMC and can support at least one channel of the 8xMCIO connector. If you know of a board that is not listed here and you would like to know if it is compatible, please <a href=https://opsero.com/contact-us target="_blank">contact us</a> .</p>Board Revision Historyhttps://docs.opsero.com/op103/datasheet/revision/Wed, 11 Feb 2026 08:13:00 -0500https://docs.opsero.com/op103/datasheet/revision/<h2 id="rev-a">Rev A</h2> <ul> <li>The MCIO PCIe FMC (OP103) is an upgrade of the original MCIO PCIe Host FMC (OP100) product which is now discontinued.</li> <li>Date of first manufacture: 2026-02-23</li> <li>Commercially released</li> </ul>