Detailed Description

Hardware Overview#

The figure below illustrates the various hardware components that are located on the top-side of the MCIO PCIe FMC.

The main components on the top-side of the mezzanine card are:

• 8xMCIO Connector
• High Pin Count FMC Connector
• 2K EEPROM
• 2x 100MHz Clock oscillators
• 2x PCIe Redrivers
• Level translators

The figure below illustrates the various hardware components that are located on the bottom-side of the mezzanine card.

The main components on the bottom-side of the mezzanine card are:

• FMC Power indicator LED
• Redriver decoupling capacitors
• Test points for power supplies

MCIO connector#

The Amphenol ICC, 8xMCIO Connector, G97R22312HR , has 8 gigabit transceiver lanes that can be used as two 4-lane links, or as a single 8-lane link. Although the connector and mezzanine card are optimized for PCIe links, they can be used with other serial link standards.

The MCIO connector carries two types of signals: transceiver lanes and sideband signals. Both are organized into two independent channels, A and B.

The transceiver lanes handle high-speed serial data and are labelled PER (receive) and PET (transmit). Lanes 0 through 3 belong to channel A, and lanes 4 through 7 belong to channel B.

Each channel also has its own set of sideband signals, identified by an A or B suffix:

• REFCLKA/B_P/N — Reference clock
• PERSTA/B_N — PCIe reset
• PRSNTA/B_N — Device present detect
• 2WA/B_SCL and 2WA/B_SDA — I2C clock and data
• BP_TYPEA/B — Backplane type (not used on this mezzanine card)
• CWAKEA/B_N — Clock wake (not used on this mezzanine card)

The pinout of the sideband signals on the MCIO connector depends on whether it is being used in host or device mode and is determined by a logic signal on the FMC interface. This allows the same connector to operate in both host mode and device mode, with the carrier board’s FPGA selecting the desired mode on configuration.

The pinout of the MCIO connector in each mode is shown in the table below:

The MCIO connector organizes its pins into two rows: the A-side and the B-side. The high-speed differential pairs are arranged such that the receive pairs (PER) are on the A-side and the transmit pairs (PET) are on the B-side. These assignments are consistent regardless of whether the connector is operating in host or device mode — the data lanes themselves do not change function between modes.

When an MCIO cable connects two devices, it crosses the A-side of one connector to the B-side of the other, and vice versa. This crossover is what establishes the correct TX-to-RX routing required by PCIe: the transmit pairs (PET) from one end of the cable arrive at the receive pairs (PER) of the other end, and the same applies in the opposite direction. No additional switching of the high-speed data lanes is needed.

However, the cable crossover also affects the sideband signals that occupy specific pin positions alongside the data lanes. In a standard PCIe connection, certain sideband signals are outputs on the host side and inputs on the device side. For example, the reference clock (REFCLK) is provided by the host, while the reset signal (PERST_N) is driven by the host toward the device. The presence detect (PRSNT_N) signal, on the other hand, is driven by the device toward the host. Because the cable swaps A-side and B-side pins, these sideband signals naturally land on the correct pins at each end — but only if the connector is wired for the appropriate mode.

Since the MCIO PCIe FMC supports both host and device modes through the same connector, the sideband pins must serve a dual purpose. In host mode, the A-side sideband pins carry host-sourced signals such as REFCLK and the B-side carries device-sourced signals such as PERST_N and PRSNT_N. In device mode, these roles are reversed to match what the remote host expects to see at the other end of the cable. The mezzanine card manages this by using multiplexers on the sideband pins, controlled by a mode selection logic signal on the FMC interface, which routes the correct signals to the correct pins based on the selected operating mode.

High-speed Switches#

The mezzanine card uses several high-speed switches ( TI, 480Mbps MUX/DEMUX Switch, TMUXHS221NKGR ) to allow the sideband signals to be switched between host and device mode. Each switch determines the purpose of a single sideband pair. For example, pair A11/A12 connects to clock oscillator output in host mode, while in device mode it connects to PERSTA_N and CPRSNTA_N. The SEL input of all switches is connected to the HOST_MODE_N signal that is driven by the FPGA.

EEPROM#

The EEPROM ( Microchip, 2Kbit EEPROM, 34AA02T-I/OT ) stores IPMI FRU data that can be read by the carrier board and contains the following information:

• Manufacturer name (Opsero Electronic Design Inc.)
• Product name
• Product part number
• Serial number
• Power supply requirements

The FRU data is read by some carrier boards to determine the correct VADJ voltage to apply to the mezzanine card. All Opsero FMC products have their EEPROMs programmed with valid FRU data to allow these carrier boards to correctly power them.

High Pin Count FMC Connector#

The MCIO PCIe FMC has a high pin count (HPC) FMC (FPGA Mezzanine Card) connector for interfacing with an FPGA or SoC development board. The part number of this connector is Samtec, High pin count FMC connector, Module side, ASP-134488-01 . This HPC FMC connector can be mated with LPC, HPC or FMC+ carrier connectors.

The pinout of this connector conforms to the VITA 57.1 FPGA Mezzanine Card Standard (for more information, see Pin configuration. For more information on the FMC connector and the VITA 57.1 standard, see the Samtec page on VITA 57.1 .

I/O Interfaces#

The FMC connector provides power to the MCIO PCIe FMC and also presents the following I/O signals to the FPGA fabric of the development board:

• 8x gigabit transceivers
• PERSTA_N and PERSTB_N active-low reset signals for channel A and B (driven by FPGA in host mode, driven by MCIO in device mode)
• PRSNTA_N and PRSNTB_N active-low present signals for channel A and B (driven by MCIO in host mode, driven by FPGA in device mode)
• SBA_DISABLE and SBB_DISABLE active-high signals to disable sidebands for channel A and B
• HOST_MODE_N for selecting between host and device modes
• LOCAL_CLKS_N for selecting the FPGA clock source between local clock and MCIO clock (in device mode only)
• 2x LVDS 100MHz reference clocks
• I2C for FMC EEPROM
• I2C for MCIO Channel-A
• I2C for MCIO Channel-B
• I2C for Redriver configuration

Host Mode#

The figure below illustrates the main connections to the FMC connector in host mode (HOST_MODE_N = LOW, LOCAL_CLKS_N = LOW). For clarity we have left out the switches and level translators from the diagram.

Device Mode#

The figure below illustrates the main connections to the FMC connector in device mode (HOST_MODE_N = HIGH, LOCAL_CLKS_N = HIGH). For clarity we have left out the switches and level translators from the diagram.

Gigabit Transceivers#

The 8x PCIe lanes of the MCIO connector are routed to FMC pins that are dedicated to gigabit transceivers. The first four lanes are referred to as channel A, while the second four lanes are referred to as channel B (not to be confused with row-A and row-B of the MCIO connector). The connections are shown in the tables below.

MCIO Channel A#

MCIO Channel B#

Reference clocks#

The mezzanine card has two clock oscillators ( MicroChip, 2x Output PCIe Clock Generator, DSC557-0334FI1 ), one for each MCIO channel. Each clock oscillator generates two synchronous 100MHz clocks; one LVDS and the other HCSL. The LVDS clocks are intended for driving the GT ref clocks, while the HCSL clocks are intended for the MCIO.

The GT ref clocks can be driven either by the on-board clock oscillators (locally) or by the remote clocks supplied by the connected MCIO host (when used in device mode). The clocks are selected by driving the LOCAL_CLKS_N signal (see below for more information on this signal).

When used in host mode, the GT ref clocks must be driven with the local clocks (LOCAL_CLKS_N = LOW). When used in device mode, it is typical to use the remote clock provided by the connected MCIO host to drive the GT ref clocks (LOCAL_CLKS_N = HIGH).

PERST_N#

The PERSTA_N and PERSTB_N signals are active-low reset signals for MCIO channels A and B respectively. They are driven by the FPGA in host mode, and driven by the MCIO link partner in device mode. Level translators convert these signals from VADJ levels (FPGA side) to 3.3V levels (MCIO side). The function of these signals is shown in the table below:

Pull-up resistors are tied to these signals on the mezzanine card on the 3.3V side so that they are not left floating if in device mode and the MCIO cable is disconnected.

Pull-up resistors are tied to these signals on the mezzanine card on the VADJ side so that they are not left floating if in host mode and the pins have not been connected in the FPGA design.

PRSNT_N#

The PRSNTA_N and PRSNTB_N signals are active-low signals driven by the MCIO device to indicate presence. In host mode, the FPGA can read this signal to determine if an MCIO device is connected. In device mode, the FPGA should drive this signal LOW to indicate its presence to the MCIO host. The functionality of these signals is described in the table below:

Pull-up resistors are tied to these signals on the mezzanine card so that they default to HIGH when in host mode and the MCIO cable is disconnected.

Pull-down resistors are tied to these signals on the mezzanine card on the VADJ side so that they are not left floating if in device mode and the pins have not been connected in the FPGA design.

HOST_MODE_N#

The HOST_MODE_N signal is an active-low signal that determines whether the mezzanine card is in host or device mode. When driven LOW, the mezzanine card is configured for host mode. When driven HIGH, the mezzanine card is configured for device mode.

LOCAL_CLKS_N#

The LOCAL_CLKS_N signal is an active-low signal that determines whether the gigabit transceiver reference clocks will be driven by local or remote clock sources. When used in device mode, we can choose to drive the GT ref clocks with the local clocks generated by the mezzanine card’s 100MHz clock oscillators, or with the remote clocks provided by the connected MCIO host.

When driven LOW, the local clock oscillators will drive the GT reference clock inputs. When driven HIGH, the MCIO host provided clocks will drive the GT reference clock inputs. Note that when used in host mode, the local clock oscillators should always be used as the GT reference clocks and LOCAL_CLK_N should always be driven LOW.

SBx_DISABLE#

The SBA_DISABLE and SBB_DISABLE signals can be used to disable the sideband signals of MCIO channel A and B respectively. The main purpose of this feature is to allow support of the Open Compute Project M-XIO standard. For most other applications of this mezzanine card, both sideband channels should be enabled.

The MCIOx8 connector on the mezzanine card is wired for SFF-9402 standard by default. To make the connector compatible with OCP M-XIO standard, albeit without 3P3VAUX_MGMT, USB or FLEXIO support, drive the SBB_DISABLE signal HIGH to disconnect the sideband B signals.

Disabling the sideband signals of a channel leaves those MCIO pins in a high-impedance state.

Power Supplies#

All power required by the MCIO PCIe FMC is supplied by the development board through the FMC connector:

• +12VDC (not used by the mezzanine card)
• +3.3VDC
• +3.3VAUX (for powering EEPROM only)
• VADJ: +1.2VDC-3.3VDC

All devices on the mezzanine card are powered by the 3.3VDC supply of the FMC connector. The +12VDC supply of the FMC connector is not used by this mezzanine card. The VADJ supply does not power any devices but is used to provide reference to the level translators.

The 3.3VDC Supply#

The 3.3VDC supply provides power for the redrivers, the clock oscillators, the switches, the inverters, the EEPROM and the level translators.

VADJ Supply#

The adjustable voltage supply (VADJ), is the I/O voltage that is supplied by all standard FMC carriers. The MCIO PCIe FMC can accept any VADJ voltage in the range of 1.2V to 3.3V. The mezzanine card has an onboard FRU EEPROM that specifies acceptance of any VADJ voltage within the range 1.2V to 3.3V (see note below). All carriers with a power management system will read this EEPROM on power-up and apply a voltage in the range specified by the EEPROM. Note that some development boards require the VADJ voltage to be configured by a DIP switch or jumper placement, in which case we suggest that it be set to 1.8V.

Power LED and testpoints#

A single green LED on the mezzanine card is used to indicate when the required power supplies are active. The location of this LED can be seen in the labelled bottom view of the board above. The LED indicates when the FMC’s 12VDC, 3.3VDC and VADJ voltages are active.

To aid hardware debug, test points are accessible on the bottom side of the mezzanine card for the 3.3V and VADJ power supplies of the MCIO PCIe FMC.