DOCS
MCIO PCIe FMC (OP103)

Compatible Boards

The following development boards are compatible with the MCIO PCIe FMC and can support at least one channel of the 8xMCIO connector. If you know of a board that is not listed here and you would like to know if it is compatible, please contact us .

Note that we don’t currently have example designs for all of these carrier boards. For a list of carrier boards for which we do have example designs, please refer to the list of supported carriers in the reference design documentation.

Series-7 boards

CarrierFMCRef designPCIeMCIO Ch-AMCIO Ch-B
AMD Xilinx KC705 Kintex-7 Development boardHPCComing soonGen24-lanesNot supported
AMD Xilinx KC705 Kintex-7 Development boardLPCComing soonGen21-lane 1Not supported 1
AMD Xilinx VC707 Virtex-7 Development boardHPC1Coming soonGen24-lanes4-lanes
AMD Xilinx VC707 Virtex-7 Development boardHPC2Coming soonGen24-lanes4-lanes
AMD Xilinx VC709 Virtex-7 Development boardHPCComing soonGen34-lanes4-lanes
AMD Xilinx ZC706 Zynq-7000 Development boardHPCComing soonGen24-lanesNot supported 2
AMD Xilinx ZC706 Zynq-7000 Development boardLPCComing soonGen21-lane 1Not supported 1
Avnet PicoZed FMC Carrier Card V2 Zynq-7000 Development BoardLPCComing soonGen21-lane 1Not supported 1

UltraScale boards

CarrierFMCRef designPCIeMCIO Ch-AMCIO Ch-B
AMD Xilinx KCU105 Kintex UltraScale Development boardHPCComing soonGen34-lanes4-lanes
AMD Xilinx KCU105 Kintex UltraScale Development boardLPCComing soonGen31-lane 1Not supported 1
AMD Xilinx VCU108 Virtex UltraScale Development boardHPC0❌Gen34-lanes4-lanes
AMD Xilinx VCU108 Virtex UltraScale Development boardHPC1❌Gen34-lanes4-lanes

Zynq Ultrascale+ boards

CarrierFMCRef designPCIeMCIO Ch-AMCIO Ch-B
AMD Xilinx ZCU104 Zynq UltraScale+ Development boardLPCComing soonGen31-lane 1Not supported 1
AMD Xilinx ZCU102 Zynq UltraScale+ Development boardHPC0❌Gen34-lanes 34-lanes 3
AMD Xilinx ZCU102 Zynq UltraScale+ Development boardHPC1❌Gen34-lanes 34-lanes 3
AMD Xilinx ZCU106 Zynq UltraScale+ Development boardHPC0Coming soonGen34-lanes4-lanes
AMD Xilinx ZCU106 Zynq UltraScale+ Development boardHPC1Coming soonGen31-lanesNot supported
AMD Xilinx ZCU111 Zynq UltraScale+ Development boardFMC+Coming soonGen34-lanes4-lanes
AMD Xilinx ZCU208 Zynq UltraScale+ Development boardFMC+Coming soonGen34-lanes4-lanes
Avnet UltraZed EV Carrier Zynq UltraScale+ Development boardHPCComing soonGen34-lanes4-lanes
Trenz UltraITX+ Baseboard Zynq UltraScale+ Development boardHPC❌Gen34-lanes 34-lanes 3

Ultrascale+ boards

CarrierFMCRef designPCIeMCIO Ch-AMCIO Ch-B
AMD Xilinx VCU118 Virtex UltraScale+ Development boardHPC❌Gen3Not supportedNot supported
AMD Xilinx VCU118 Virtex UltraScale+ Development boardFMC+Coming soonGen34-lanes4-lanes

Versal boards

CarrierFMCRef designPCIeMCIO Ch-AMCIO Ch-B
AMD Xilinx VCK190 Versal AI Core Development boardFMC+1Coming soonGen44-lanes4-lanes
AMD Xilinx VCK190 Versal AI Core Development boardFMC+2Coming soonGen44-lanes4-lanes
AMD Xilinx VEK280 Versal AI Edge Development boardFMC+Coming soonGen44-lanes4-lanes
AMD Xilinx VHK158 Versal HBM Series Development boardFMC+Coming soonGen44-lanesNot supported 4
AMD Xilinx VMK180 Versal Prime Series Development boardFMC+1Coming soonGen44-lanes4-lanes
AMD Xilinx VMK180 Versal Prime Series Development boardFMC+2Coming soonGen44-lanes4-lanes
AMD Xilinx VPK120 Versal Premium Series Development boardFMC+Coming soonGen44-lanesNot supported 4
AMD Xilinx VPK180 Versal Premium Series Development boardFMC+Coming soonGen44-lanesNot supported 4

Compatibility requirements

If you need to determine the compatibility of a development board that is not listed here, or you are designing a carrier board to mate with the MCIO PCIe FMC, you can check your board against the list of requirements below.

VADJ

The carrier board must have the ability to supply a VADJ voltage between 1.2VDC and 3.3VDC.

Gigabit transceivers

The FPGA or MPSoC device must have gigabit transceivers and they must be routed to the FMC connector. For support of both MCIO channels, transceivers DP0-DP7 must all be connected to the FPGA. In the AMD Xilinx devices, the transceivers are typically grouped into quads containing 4 transceivers. Ideally, each MCIO channel should be connected to a single quad and the lane ordering should match the MGT ordering as shown in the tables below:

Quad 1

The first quad should be connected to MCIO Channel-A as follows:

FPGA pinPCIe laneFMC PinFMC nameNet name
MGT_RXP/N00C6/C7DP0_M2C_P/NPERA_0_P/N
MGT_TXP/N00C2/C3DP0_C2M_P/NPETA_0_P/N
MGT_RXP/N11A2/A3DP1_M2C_P/NPERA_1_P/N
MGT_TXP/N11A22/A23DP1_C2M_P/NPETA_1_P/N
MGT_RXP/N22A6/A7DP2_M2C_P/NPERA_2_P/N
MGT_TXP/N22A26/A27DP2_C2M_P/NPETA_2_P/N
MGT_RXP/N33A10/A11DP3_M2C_P/NPERA_3_P/N
MGT_TXP/N33A30/A31DP3_C2M_P/NPETA_3_P/N

The clock reference for this channel (FMC pins GBTCLK0_M2C_P/N) should be connected to MGTREFCLK0P/N or MGTREFCLK1P/N of this quad.

Quad 2

The second quad should be connected to MCIO Channel-B as follows:

DirectionPCIe laneFMC PinFMC nameNet name
MGT_RXP/N00A14/A15DP4_M2C_P/NPERB_0_P/N
MGT_TXP/N00A34/A35DP4_C2M_P/NPETB_0_P/N
MGT_RXP/N11A18/A19DP5_M2C_P/NPERB_1_P/N
MGT_TXP/N11A38/A39DP5_C2M_P/NPETB_1_P/N
MGT_RXP/N22B16/B17DP6_M2C_P/NPERB_2_P/N
MGT_TXP/N22B36/B37DP6_C2M_P/NPETB_2_P/N
MGT_RXP/N33B12/B13DP7_M2C_P/NPERB_3_P/N
MGT_TXP/N33B32/B33DP7_C2M_P/NPETB_3_P/N

The clock reference for this channel (FMC pins GBTCLK1_M2C_P/N) should be connected to MGTREFCLK0P/N or MGTREFCLK1P/N of this quad.

Reference clocks

The mezzanine card generates two 100MHz reference clocks and supplies them to the carrier board via pins GBTCLK0_M2C_P/N and GBTCLK1_M2C_P/N of the FMC connector. The reference clocks are intended to clock the gigabit transceivers and are standard LVDS signals as required by VITA 57.1 Rule 5.54. The gigabit transceivers in AMD Xilinx devices support LVDS reference clocks. For devices of other manufacturers, please ensure that the reference clock inputs of the gigabit transceivers can support the LVDS signaling standard.

Required I/O

The following I/O pins should be connected to the FPGA as they are required by the mezzanine card:

FMC PinFMC nameNetDescription
G6LA00_P_CCPERSTA_N_TPCIe reset for MCIO Channel A (active low)
G7LA00_N_CCCPRSNTA_N_TPresent for MCIO Channel A (active low)
H10LA04_PPERSTB_N_TPCIe reset for MCIO Channel B (active low)
H11LA04_NCPRSNTB_N_TPresent for MCIO Channel B (active low)
C14LA10_PSBA_DISABLE_TDisable sideband A signals
C15LA10_NSBB_DISABLE_TDisable sideband B signals
C18LA14_PHOST_MODE_N_THost mode enable active-low (0:HOST MODE, 1:DEVICE MODE)
C19LA14_NLOCAL_CLKS_N_TLocal/remote clock select (0:LOCAL, 1:REMOTE)
G15LA12_PMCIOA_I2C_SCLI2C clock for MCIO Channel A
G16LA12_NMCIOA_I2C_SDAI2C data for MCIO Channel A
H16LA11_PMCIOB_I2C_SCLI2C clock for MCIO Channel B
H17LA11_NMCIOB_I2C_SDAI2C data for MCIO Channel B
H19LA15_PRDRV_I2C_SCLI2C clock for Redrivers
H20LA15_NRDRV_I2C_SDAI2C data for Redrivers

  1. LPC connectors can only support 1-lane PCIe ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎

  2. Zynq-7000 devices only have 1 PCIe block ↩︎

  3. This board’s device does not have integrated PCIe blocks, but it can be used with 3rd party IP to implement the required PCIe root complex ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎

  4. VHK150, VPK120 and VPK180 boards have enough PCIe blocks and GTs to support both MCIO channels, however one of the PCIe blocks is located on the opposite side of the device to the relevant GTs, making routing a challenge. For this reason we do not support the use of MCIO Channel B on these boards. ↩︎ ↩︎ ↩︎

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