Example Designs

Mon, 23 Feb 2026 00:00:00 -0500

The example designs for the Quad SFP28 FMC are hosted on Github.

Example Designs
10G/25G Ethernet Subsystem Example Design	More info	Git repo	Docs
10G/25G Ethernet MRMAC Example Design	More info	Git repo	Docs

10G/25G Ethernet Subsystem based example

Description

This example design is based on Xilinx’s soft MAC (ie. FPGA implemented), the AMD Xilinx 10G/25G Ethernet Subsystem IP , that can be found in the Vivado IP Catalog. As the MAC is implemented in the FPGA fabric, this example is ideal for pure FPGA designs or Zynq/ZynqMP designs that require some packet processing to be performed in the FPGA.

Board Files

Mon, 23 Feb 2026 00:00:00 -0500

Board Files

Rev-A

Quad SFP28 FMC Rev-A Schematics PDF
Quad SFP28 FMC Rev-A Assembly Drawing PDF
Quad SFP28 FMC Rev-A 3D STEP model

Part Datasheets

Use the links below to access the datasheets of the significant parts on the mezzanine card.

Resources on Opsero Docs

Example Designs

10G/25G Ethernet Subsystem based example

Description

Board Files

Board Files

Rev-A

Part Datasheets