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Example Designs
The example designs for the Quad SFP28 FMC are hosted on Github.
| Example Designs | |||
|---|---|---|---|
| 10G/25G Ethernet Subsystem Example Design | More info | Git repo | Docs |
| 10G/25G Ethernet MRMAC Example Design | More info | Git repo | Docs |
| IBERT Loopback Test Designs | More info | Git repo | Docs |
10G/25G Ethernet Subsystem based example
Description
This example design is based on AMD’s soft MAC (ie. FPGA implemented), the AMD Xilinx 10G/25G Ethernet Subsystem IP , that can be found in the Vivado IP Catalog. As the MAC is implemented in the FPGA fabric, this example is ideal for pure FPGA designs or Zynq/ZynqMP designs that require some packet processing to be performed in the FPGA. Each of the four SFP28 ports has its own 10G/25G Ethernet Subsystem over a GTY transceiver, with packet data moved to and from DDR by an AXI DMA, and the ports are driven under Linux (PetaLinux) by the AXI Ethernet driver.
Note that this example design was developed using the AMD Xilinx tools and the
AMD Xilinx 10G/25G Ethernet Subsystem IP . If you wish to use this example design, you must at least have an evaluation license for that IP. See instructions on obtaining a license here.
Links
Block diagrams
Zynq UltraScale+ designs
Versal designs
Supported carrier boards
- Avnet UltraZed EV Carrier Zynq UltraScale+ Development board
- AMD Xilinx ZCU102 Zynq UltraScale+ Development board
- AMD Xilinx ZCU104 Zynq UltraScale+ Development board
- AMD Xilinx ZCU106 Zynq UltraScale+ Development board
- AMD Xilinx ZCU111 Zynq UltraScale+ Development board
- AMD Xilinx ZCU208 Zynq UltraScale+ Development board
- AMD Xilinx ZCU216 Zynq UltraScale+ Development board
- AMD Xilinx VCK190 Versal AI Core Development board
- AMD Xilinx VMK180 Versal Prime Series Development board
- AMD Xilinx VEK280 Versal AI Edge Development board
- AMD Xilinx VHK158 Versal HBM Series Development board
- AMD Xilinx VPK120 Versal Premium Series Development board
- AMD Xilinx VPK180 Versal Premium Series Development board
10G/25G Ethernet (MRMAC) based example
Description
This example design uses the AMD Xilinx Versal Integrated 100G Multirate Ethernet MAC (MRMAC) , a hardened block found in AMD Versal adaptive SoC devices, configured as four independent 10GbE or 25GbE channels (one GTY lane per port). Each port is served by its own AXI MCDMA for moving packet data to and from DDR through the NoC, and the ports are driven under Linux (PetaLinux) by the AXI Ethernet driver. A bare-metal echo-server test application is also included. As the MAC is a hardened block, this example frees up FPGA fabric resources and is ideal for high-bandwidth Versal-based designs.
Links
Block diagram
Supported carrier boards
- AMD Xilinx VCK190 Versal AI Core Development board
IBERT loopback test designs
Description
These projects test the Quad SFP28 FMC in loopback using the AMD IBERT (Integrated Bit Error Ratio Tester) core, with either active or passive loopback modules in the SFP28 cages. They let you run eye scans and measure the link quality of all four lanes at 10G and 28G line rates. We use these projects internally for development and production test, but feel free to use them to build your own similar test setups. The same repository also contains IBERT designs for our other transceiver-based FMCs.
Links
Supported carrier boards
- AMD Xilinx VCK190 Versal AI Core Development board (FMCP1)
- AMD Xilinx VEK280 Versal AI Edge Development board
PS GEM based example
Description
This example design utilizes the Gigabit Ethernet MACs (GEMs) that are embedded into the Processing System (PS) of the Zynq 7000™ and Zynq Ultrascale+™ devices. The embedded MACs used in this example design do not use up any of the FPGA fabric, which makes it ideal for applications that need to use the FPGA for other purposes.
Links
- Coming soon