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Example Designs
The example designs for the Quad SFP28 FMC are hosted on Github.
| Example Designs | |||
|---|---|---|---|
| 10G/25G Ethernet Subsystem Example Design | More info | Git repo | Docs |
| 10G/25G Ethernet MRMAC Example Design | More info | Git repo | Docs |
10G/25G Ethernet Subsystem based example
Description
This example design is based on Xilinx’s soft MAC (ie. FPGA implemented), the AMD Xilinx 10G/25G Ethernet Subsystem IP , that can be found in the Vivado IP Catalog. As the MAC is implemented in the FPGA fabric, this example is ideal for pure FPGA designs or Zynq/ZynqMP designs that require some packet processing to be performed in the FPGA.
Note that this example design was developed using Xilinx software tools and the
AMD Xilinx 10G/25G Ethernet Subsystem IP . If you wish to use this example design, you must at least have an evaluation license for that IP. See instructions on obtaining a license here.
Links
Block diagrams
Zynq UltraScale+ designs
Versal designs
10G/25G Ethernet (MRMAC) based example
Description
This example design uses the Versal Integrated 100G Multirate Ethernet MAC (MRMAC), a hardened block found in AMD Versal adaptive SoC devices, configured as four independent 10GbE or 25GbE channels. Each port is served by its own AXI MCDMA for moving packet data to and from DDR. As the MAC is a hardened block, this example frees up FPGA fabric resources and is ideal for high-bandwidth Versal-based designs.
Links
PS GEM based example
Description
This example design utilizes the Gigabit Ethernet MACs (GEMs) that are embedded into the Processing System (PS) of the Zynq 7000™ and Zynq Ultrascale+™ devices. The embedded MACs used in this example design do not use up any of the FPGA fabric, which makes it ideal for applications that need to use the FPGA for other purposes.
Links
- Coming soon