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Programming Guide
This section provides the details of the programming requirements to operate the Ethernet FMC hardware and customise functionality.
SFP I/Os
Some of the SFP I/Os must be driven by the FPGA to fixed levels in order to configure the SFP/SPF+/SFP28 modules for normal operation.
Optical output
SFP module input TX_DISABLE allows the FPGA to disable the optical output if so desired. In normal operation however, this input should be driven LOW to enable optical output.
| Net | Description | FMC pin | Value for normal operation |
|---|---|---|---|
| SFP0_TX_DISABLE_T | Slot 0: Disables optical output | LA03_P | LOW (0) |
| SFP1_TX_DISABLE_T | Slot 1: Disables optical output | LA12_P | LOW (0) |
| SFP2_TX_DISABLE_T | Slot 2: Disables optical output | LA15_N | LOW (0) |
| SFP3_TX_DISABLE_T | Slot 3: Disables optical output | LA17_CC_N | LOW (0) |
Note that the pins in the above table must not be left floating. If your SFP modules do not require
these signals to be driven, we recommend that you drive them LOW to ensure that the inputs to the
level translators are not left floating.
Rate select
The SFP module inputs, RS0 and RS1, generally allow the FPGA to configure the module for different link speeds or performance levels. However, their specific function may vary by vendor. Please refer to the datasheet of your SFP/SFP+/SFP28 module for detailed information on configuring these pins. Note that some modules do not use these pins at all.
If you are unsure what levels to apply to RS0 and RS1, or if your modules do not require them, we recommend driving the signals to the constant values shown in the table below.
| Net | Description | FMC pin | Value |
|---|---|---|---|
| SFP0_RS1_T | Slot 0: Rate select 1 | LA02_P | LOW (0) |
| SFP0_RS0_T | Slot 0: Rate select 0 | LA02_N | LOW (0) |
| SFP1_RS1_T | Slot 1: Rate select 1 | LA08_P | LOW (0) |
| SFP1_RS0_T | Slot 1: Rate select 0 | LA08_N | LOW (0) |
| SFP2_RS1_T | Slot 2: Rate select 1 | LA10_P | LOW (0) |
| SFP2_RS0_T | Slot 2: Rate select 0 | LA10_N | LOW (0) |
| SFP3_RS1_T | Slot 3: Rate select 1 | LA14_P | LOW (0) |
| SFP3_RS0_T | Slot 3: Rate select 0 | LA14_N | LOW (0) |
Note that the pins in the above table must not be left floating. If your SFP modules do not require
these signals to be driven, we recommend that you drive them LOW to ensure that the inputs to the
level translators are not left floating.
I2C Switch
The I2C switch ( PCA9548 ) is connected to the PS I2C bus and allows the FPGA to communicate with the SFP/SFP+/SFP28 modules and the jitter-attenuating clock multiplier. The I2C switch has address 0x70.
| A6 | A5 | A4 | A3 | A2 | A1 | A0 | Hexadecimal |
|---|---|---|---|---|---|---|---|
| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0x70 |
The PS I2C bus signals are connected to the FMC pins listed in the table below:
| Net Name | Description | FMC pin |
|---|---|---|
| PL_I2C_SCL_T | I2C clock (SCL) | LA11_P |
| PL_I2C_SDA_T | I2C data (SDA) | LA11_N |
The channels of the I2C switch are connected as shown in the table below:
| I2C Device | Switch channel | Device I2C address |
|---|---|---|
| SFP28 Slot 0 | 0 | Module dependent |
| SFP28 Slot 1 | 1 | Module dependent |
| SFP28 Slot 2 | 2 | Module dependent |
| SFP28 Slot 3 | 3 | Module dependent |
| Clock multiplier | 4 | 0x68 |
Note that the I2C addresses of the SFP/SFP+/SFP28 modules are dependent on the specific module used. Refer to the module datasheet for this information.
Clock multiplier
The jitter-attenuating clock multiplier ( Skyworks, Si5328 ) must be configured via the PS I2C bus to enable appropriate clocks for the SFP/SFP+/SFP28 modules used. The Si5328 has the I2C address 0x68.
| A6 | A5 | A4 | A3 | A2 | A1 | A0 | Hexadecimal |
|---|---|---|---|---|---|---|---|
| 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0x68 |
Refer to the Si5328 datasheet for detailed information on the device registers and how to configure the clock outputs.
EEPROM
The 2K EEPROM is intended to store information that identifies the mezzanine card and also specifies the power supplies required by the card. This information is typically read by the system power management on the carrier board when it is powered up. In typical user applications, it should not be necessary to read the data on the EEPROM, and we highly recommend against writing to the EEPROM. Nevertheless, if you wish to access the EEPROM, it can be read and written to at the I2C address 0x50.
| A6 | A5 | A4 | A3 | A2 | A1 | A0 | Hexadecimal |
|---|---|---|---|---|---|---|---|
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0x50 |
The EEPROM sits on the FMC card’s dedicated I2C bus. The FMC pins of the EEPROM’s I2C bus are shown below, and it is up to the user to determine their corresponding connections to the FPGA/MPSoC on the carrier board being used.
| I2C bus signal | FMC pin name | FMC pin number |
|---|---|---|
| SCL (clock) | SCL | C30 |
| SDA (data) | SDA | C31 |
Be aware that on some carrier boards, the FMC I2C bus passes through an I2C MUX. On some boards it connects to
FPGA pins whereas on others it connects to PS pins. If you wish to communicate with the EEPROM, it is necessary
to check the schematic drawing of your carrier board to determine the structure of the I2C bus and to which
pins it connects.
Restoring contents
If you need to reprogram the EEPROM with the original factory contents, you can use the Opsero FMC EEPROM Tool.