Example Designs

Mon, 23 Feb 2026 00:00:00 -0500

The example designs for the Ethernet FMC Max are hosted on Github.

Example Designs
AXI 1G Ethernet Example Design	More info	Git repo	Docs

Note that all of our example designs were developed using Xilinx software tools and the Xilinx AXI Ethernet Subsystem IP. If you wish to use these example designs, you must at least have an evaluation license for the Xilinx TEMAC IP. See instructions on obtaining a license here.

AXI 1G Ethernet Subsystem based example

Description

This example design is based on Xilinx’s soft MAC (ie. FPGA implemented), the AMD Xilinx AXI 1G/2.5G Ethernet Subsystem IP , that can be found in the Vivado IP Catalog. As the MAC is implemented in the FPGA fabric, this example is ideal for pure FPGA designs or Zynq/ZynqMP designs that require some packet processing to be performed in the FPGA.

Resources on Opsero Docs

Example Designs

AXI 1G Ethernet Subsystem based example

Description

Board Files

Board Files

Rev-A

Rev-B

Part Datasheets