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Example Designs
The example designs for the Ethernet FMC Max are hosted on Github.
| Example Designs | |||
|---|---|---|---|
| AXI 1G Ethernet Example Design | More info | Git repo | Docs |
| PS GEM Example Design | More info | Git repo | Docs |
| FPGA Packet Recorder (in development) | More info | Git repo | Docs |
Note that the AXI Ethernet based example design was developed using the AMD Xilinx tools and the
AMD AXI Ethernet Subsystem IP. If you wish to use that example design, you must at least
have an evaluation license for the AMD TEMAC IP. See instructions on
obtaining a license here.
The PS GEM based example uses the hard MACs of the processing system and the license-free
PCS/PMA core, so it needs no IP license.
AXI 1G Ethernet Subsystem based example
Description
This example design is based on AMD’s soft MAC (ie. FPGA implemented), the AMD Xilinx AXI 1G/2.5G Ethernet Subsystem IP , that can be found in the Vivado IP Catalog. As the MAC is implemented in the FPGA fabric, this example is ideal for pure FPGA designs or Zynq/ZynqMP designs that require some packet processing to be performed in the FPGA. Each of the four ports has its own AXI Ethernet Subsystem in SGMII mode and an AXI DMA. The design comes with an lwIP echo server bare-metal application and a Linux (PetaLinux) flow, and it targets MicroBlaze, Zynq UltraScale+ and Versal development boards.
Links
Block diagram
Supported carrier boards
- Tria AUBoard 15P Artix UltraScale+ Development board
- AMD Xilinx KCU105 Kintex UltraScale Development board
- AMD Xilinx VCU118 Virtex UltraScale+ Development board
- Avnet UltraZed EV Carrier Zynq UltraScale+ Development board
- AMD Xilinx ZCU102 Zynq UltraScale+ Development board
- AMD Xilinx ZCU104 Zynq UltraScale+ Development board
- AMD Xilinx ZCU106 Zynq UltraScale+ Development board
- AMD Xilinx ZCU111 Zynq UltraScale+ Development board
- AMD Xilinx ZCU208 Zynq UltraScale+ Development board
- AMD Xilinx ZCU216 Zynq UltraScale+ Development board
- AMD Xilinx VCK190 Versal AI Core Development board
- AMD Xilinx VMK180 Versal Prime Series Development board
- AMD Xilinx VEK280 Versal AI Edge Development board
- AMD Xilinx VHK158 Versal HBM Series Development board
- AMD Xilinx VPK120 Versal Premium Series Development board
- AMD Xilinx VPK180 Versal Premium Series Development board
PS GEM based example
Description
This example design utilizes the Gigabit Ethernet MACs (GEMs) that are embedded into the Processing System (PS) of the Zynq UltraScale+ and Versal devices. Each port of the Ethernet FMC Max is driven by a PS GEM routed through EMIO GMII into the programmable logic, where a AMD Xilinx 1G/2.5G Ethernet PCS/PMA or SGMII IP core converts the GMII to SGMII over a gigabit transceiver lane connected to the port’s TI DP83867 PHY. No soft MAC or DMA IP is used: the ports are handled by the standard PS GEM software drivers, in bare-metal (lwIP echo server) or in Linux (PetaLinux). The embedded MACs do not use up any of the FPGA fabric, which makes this design ideal for applications that need the FPGA for other purposes.
Links
Block diagrams
Zynq UltraScale+ designs
Versal designs
Supported carrier boards
- Avnet UltraZed EV Carrier Zynq UltraScale+ Development board
- AMD Xilinx ZCU102 Zynq UltraScale+ Development board
- AMD Xilinx ZCU106 Zynq UltraScale+ Development board
- AMD Xilinx ZCU111 Zynq UltraScale+ Development board
- AMD Xilinx VCK190 Versal AI Core Development board
FPGA Packet Recorder
This design is still in development. The repository is public and development is in
progress on the
dev branch, but it is not yet released or documented.Description
This design turns a ZCU106 fitted with the Ethernet FMC Max (on HPC0) and the FPGA Drive FMC Gen4 (on HPC1) into a lossless, hardware-timestamped Gigabit Ethernet packet capture and replay tool. Capture runs entirely in the FPGA fabric and records straight to an NVMe SSD using the zero-copy datapath of the FPGA Drive Recorder. Every frame is timestamped in hardware from the PHYs’ start-of-frame signals against one shared timebase. The four ports work as two transparent inline taps (P0-P1, P2-P3) or as four independent monitor inputs, selectable at runtime. A web interface on the board’s own Ethernet port starts and stops captures and serves them as pcapng files that open directly in Wireshark. Captures can be replayed out of a port with their original timing.
Links
Supported carrier boards
- AMD Xilinx ZCU106 Zynq UltraScale+ Development board