Programming Guide

This section provides the details of the programming requirements to operate the Ethernet FMC Max hardware and customise functionality.

Required PHY settings#

The following PHY settings are required for correct operation of the Ethernet FMC Max. Most of them are set to the appropriate value by hardware straps or by software in our reference designs. The information in this section is provided for reference to users that are not using our reference designs and are instead developing their own custom designs and software.

Mirror Mode#

For correct operation of the Ethernet FMC Max, the mirror mode (bit 0, register 0x0031) must be enabled. On the Rev-A boards, this is not enabled by the strap pins and must be enabled by software.

The example code below demonstrates enabling Mirror mode for port 0 (PHY address 0x01) by making MDIO writes to register 0x0031 in the extended address space. The functions used are defined in the extended address space section. Note that similar code is already integrated into our example designs and is included here as a reference for users that are developing custom designs and software.

u16 reg;
u32 phy_addr = 0x01;
// Read the current value of the register
XAxiEthernet_PhyReadExtended(axieth_inst,phy_addr,0x0031,&reg);
// Enable Mirror mode
reg |= 0x0001;
// Write the new value to the register
XAxiEthernet_PhyWriteExtended(axieth_inst,phy_addr,0x0031,reg);

In Linux, Mirror mode can be enabled by adding the enet-phy-lane-swap property to the PHY nodes as shown below:

&axi_ethernet_0 {
    local-mac-address = [00 0a 35 00 01 22];
    phy-handle = <&extphy0>;
    xlnx,has-mdio = <0x1>;
    phy-mode = "sgmii";
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        extphy0: phy@1 {
            device_type = "ethernet-phy";
            reg = <1>;
            xlnx,phy-type = <0x4>;
            ti,fifo-depth = <0x1>;
            enet-phy-lane-swap;
        };
        extphy1: phy@3 {
            device_type = "ethernet-phy";
            reg = <3>;
            xlnx,phy-type = <0x4>;
            ti,fifo-depth = <0x1>;
            enet-phy-lane-swap;
        };
        extphy2: phy@12 {
            device_type = "ethernet-phy";
            reg = <12>;
            xlnx,phy-type = <0x4>;
            ti,fifo-depth = <0x1>;
            enet-phy-lane-swap;
        };
        extphy3: phy@15 {
            device_type = "ethernet-phy";
            reg = <15>;
            xlnx,phy-type = <0x4>;
            ti,fifo-depth = <0x1>;
            enet-phy-lane-swap;
        };
    };
};

PHY registers#

The functionality of the TI DP83867 Gigabit Ethernet PHYs can be customized by writing to the registers of the device via the MDIO bus. These registers are detailed in the DP83867 datasheet .

To target a specific PHY for an MDIO transaction, use the MDIO addresses listed in the table below:

The tables below list some of the registers and settings that are useful for basic operation of the Ethernet FMC Max. For a comprehensive list of the registers, please refer to the DP83867 datasheet .

Basic Mode Control Register (BMCR), Address 0x0000#

Basic Mode Status Register (BMSR), Address 0x0001#

Auto-Negotiation Advertisement Register (ANAR), Address 0x0004#

Configuration Register 1 (CFG1), Address 0x0009#

PHY Control Register (PHYCR), Address 0x0010#

The SGMII enable setting is set to 1 by strap resistors on the Ethernet FMC Max; it does not need to be set by software.

PHY Status Register (PHYSTS), Address 0x0011#

Interrupt Status Register (ISR), Address 0x0013#

Configuration Register 2 (CFG2), Address 0x0014#

Configuration Register 4 (CFG4), Address 0x0031#

SGMII Control Register 1 (SGMIICTL1), Address 0x00D3#

The SGMII Configuration should be set to 0x0 (4-wire mode) for the Ethernet FMC Max. This is the default setting and does not require setting by software.

Extended Address Space Access#

All PHY registers above address 0x001F are in the extended address space and must be accessed using registers REGCR (0x000D) and ADDAR (0x000E). The procedure for accessing registers in the extended address space is described in the DP83867 datasheet . The code snippets below can be used as examples of reading and writing to the extended register space:

Extended Register Read Function#

// Read from PHY extended register (address above 0x001F)

void XAxiEthernet_PhyReadExtended(XAxiEthernet *InstancePtr, u32 PhyAddress,
                                  u32 RegisterNum, u16 *PhyDataPtr)
{
	XAxiEthernet_PhyWrite(InstancePtr, PhyAddress,TI_PHY_REGCR, 0x001F);
	XAxiEthernet_PhyWrite(InstancePtr, PhyAddress,TI_PHY_ADDDR, RegisterNum);
	XAxiEthernet_PhyWrite(InstancePtr, PhyAddress,TI_PHY_REGCR, 0x401F);
	XAxiEthernet_PhyRead(InstancePtr, PhyAddress,TI_PHY_ADDDR, PhyDataPtr);
}

Extended Register Write Function#

// Write to PHY extended register (address above 0x001F)

void XAxiEthernet_PhyWriteExtended(XAxiEthernet *InstancePtr, u32 PhyAddress,
                                   u32 RegisterNum, u16 PhyDataPtr)
{
	XAxiEthernet_PhyWrite(InstancePtr, PhyAddress,TI_PHY_REGCR, 0x001F);
	XAxiEthernet_PhyWrite(InstancePtr, PhyAddress,TI_PHY_ADDDR, RegisterNum);
	XAxiEthernet_PhyWrite(InstancePtr, PhyAddress,TI_PHY_REGCR, 0x401F);
	XAxiEthernet_PhyWrite(InstancePtr, PhyAddress,TI_PHY_ADDDR, PhyDataPtr);
}

EEPROM#

The 2K EEPROM is intended to store information that identifies the mezzanine card and also specifies the power supplies required by the card. This information is typically read by the system power management on the carrier board when it is powered up. In typical user applications, it should not be necessary to read the data on the EEPROM, and we highly recommend against writing to the EEPROM. Nevertheless, if you wish to access the EEPROM, it can be read and written to at the I2C address 0x50.

The EEPROM sits on the FMC card’s dedicated I2C bus. The FMC pins of the EEPROM’s I2C bus are shown below, and it is up to the user to determine their corresponding connections to the FPGA/MPSoC on the carrier board being used.

Restoring contents#

If you need to reprogram the EEPROM with the original factory contents, you can use the Opsero FMC EEPROM Tool.