https://docs.opsero.com/op080/datasheet/Recent content in Datasheet on Opsero DocsHugoenCopyright (c) 2026 Opsero Electronic Design Inc.Mon, 23 Feb 2026 00:00:00 -0500https://docs.opsero.com/op080/datasheet/overview/Mon, 23 Feb 2026 00:00:00 -0500https://docs.opsero.com/op080/datasheet/overview/<h2 id="description">Description</h2> <p>The Ethernet FMC Max is an add-on/expansion board (FPGA Mezzanine Card) for FPGA and SoC based development boards. The mezzanine card has 4x Texas Instruments <a href=https://download.opsero.com/datasheet/dp83867cs.pdf target="_blank">DP83867</a> Gigabit Ethernet PHYs to provide 4 ports of gigabit Ethernet connectivity to the carrier development board.</p>https://docs.opsero.com/op080/datasheet/pin-configuration/Mon, 23 Feb 2026 00:00:00 -0500https://docs.opsero.com/op080/datasheet/pin-configuration/<h2 id="pinout-table">Pinout table</h2> <p>The Ethernet FMC Max has a high pin count FPGA Mezzanine Card (FMC) connector, providing the connections to the FPGA on the development board. The following table defines the pinout of the FMC connector and describes each pin&rsquo;s purpose on this mezzanine card.</p>https://docs.opsero.com/op080/datasheet/specifications/Mon, 23 Feb 2026 00:00:00 -0500https://docs.opsero.com/op080/datasheet/specifications/<h2 id="recommended-operating-conditions">Recommended Operating Conditions</h2> <table> <thead> <tr> <th>SUPPLY VOLTAGE</th> <th>MIN</th> <th>TYP</th> <th>MAX</th> <th>UNIT</th> </tr> </thead> <tbody> <tr> <td>12 VDC</td> <td>+11.4</td> <td>+12</td> <td>+12.6</td> <td>V</td> </tr> <tr> <td>3.3 VDC</td> <td>+3.14</td> <td>+3.3</td> <td>+3.46</td> <td>V</td> </tr> <tr> <td>VADJ (1.2VDC)</td> <td>+1.14</td> <td>+1.2</td> <td>+1.26</td> <td>V</td> </tr> <tr> <td>VADJ (1.5VDC)</td> <td>+1.425</td> <td>+1.5</td> <td>+1.575</td> <td>V</td> </tr> <tr> <td>VADJ (1.8VDC)</td> <td>+1.71</td> <td>+1.8</td> <td>+1.89</td> <td>V</td> </tr> <tr> <td>VADJ (2.5VDC)</td> <td>+2.375</td> <td>+2.5</td> <td>+2.625</td> <td>V</td> </tr> </tbody> </table> <p>Notes:</p>https://docs.opsero.com/op080/datasheet/detailed-description/Mon, 23 Feb 2026 00:00:00 -0500https://docs.opsero.com/op080/datasheet/detailed-description/<h2 id="hardware-overview">Hardware Overview</h2> <p>The figure below illustrates the various hardware components that are located on the top-side (component side) of the Ethernet FMC Max.</p>https://docs.opsero.com/op080/datasheet/mechanical/Mon, 23 Feb 2026 00:00:00 -0500https://docs.opsero.com/op080/datasheet/mechanical/<h2 id="height-profile">Height Profile</h2> <p>The figure below illustrates the height profile of the Ethernet FMC Max. All of the components on the Ethernet FMC Max fit within the 10mm gap between the FMC card and the development board.</p>https://docs.opsero.com/op080/datasheet/compatibility/Mon, 23 Feb 2026 00:00:00 -0500https://docs.opsero.com/op080/datasheet/compatibility/<p>This section of the documentation aims to list all of the development boards for which compatibility with the Ethernet FMC Max has been checked, and to list constraints and any notes concerning special requirements or limitations with the board.</p>https://docs.opsero.com/op080/datasheet/revision/Mon, 23 Feb 2026 00:00:00 -0500https://docs.opsero.com/op080/datasheet/revision/<h2 id="rev-a">Rev A</h2> <ul> <li>First board release</li> </ul> <h2 id="rev-b">Rev B</h2> <ul> <li>Added testpoint TP9 for probing VADJ voltage</li> <li>Changed LED_0 strap to MODE 4 on all PHYs (enable Mirror mode)</li> <li>Changed LED_0 (left LED) wiring to active low on all PHYs</li> </ul>