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Programming Guide
This section provides the details of the programming requirements to operate the M.2 M-key Stack FMC hardware and customise functionality.
EEPROM
The 2K EEPROM is intended to store information that identifies the mezzanine card and also specifies the power supplies required by the card. This information is typically read by the system power management on the carrier board when it is powered up. In typical user applications, it should not be necessary to read the data on the EEPROM, and we highly recommend against writing to the EEPROM.
As the M.2 M-key Stack FMC does not make use any of the FMC I/O signals, it does not require any particular voltage level to be applied to VADJ. The EEPROM was included on the mezzanine card to satisfy the VITA 57.1 standard and to ensure compatibility with all standard FMC carriers. The EEPROM is programmed to accept a VADJ voltage between 1.2V and 3.3V.
Address switching
The I2C address of the EEPROM is switched between 0x50 and 0x54, by use of the device’s A2 input pin. The device’s address depends on the presence of a second mezzanine card “stacked” on top of the M.2 M-key Stack FMC. Switching of the I2C address of the EEPROM is necessary to avoid a bus conflict with the second mezzanine card’s EEPROM.
When a second mezzanine card is “stacked” onto the M.2 M-key Stack FMC, it is the second mezzanine card’s EEPROM that will determine the VADJ voltage provided by the carrier board. To prevent the power controller from reading the EEPROM of the M.2 M-key Stack FMC in this case, it detects when a second mezzanine card is present (using the PRSNT_M2C_L signal) and changes it’s own EEPROM’s address by driving it’s A2 input HIGH.
Address without 2nd mezzanine
The EEPROM address when the M.2 M-key Stack FMC is used without a second mezzanine card.
| A6 | A5 | A4 | A3 | A2 | A1 | A0 | Hexadecimal |
|---|---|---|---|---|---|---|---|
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0x50 |
Address with 2nd mezzanine
The EEPROM address when a second mezzanine is attached.
| A6 | A5 | A4 | A3 | A2 | A1 | A0 | Hexadecimal |
|---|---|---|---|---|---|---|---|
| 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0x54 |
The addresses shown above assume that FMC signals GA0 and GA1 from the FMC carrier board are both LOW (0), which is the case
for most FPGA/MPSoC development boards. If GA0 and GA1 are not LOW, then the actual addresses can be determined by
setting A1=GA0 and A0=GA1.
The FMC pins of the EEPROM’s I2C bus are shown below, and it is up to the user to determine their corresponding connections to the FPGA/MPSoC on the carrier board being used.
| I2C bus signal | FMC pin name | FMC pin number |
|---|---|---|
| SCL (clock) | SCL | C30 |
| SDA (data) | SDA | C31 |
Be aware that on some carrier boards, the FMC I2C bus passes through an I2C MUX. On some boards it connects to
FPGA pins whereas on others it connects to PS pins. If you wish to communicate with the EEPROM, it is necessary
to check the schematic drawing of your carrier board to determine the structure of the I2C bus and to which
pins it connects.
Restoring contents
If you need to reprogram the EEPROM with the original factory contents, you can use the Opsero FMC EEPROM Tool.
Do not use the Opsero FMC EEPROM Tool with the M.2 M-key Stack FMC while it has a second mezzanine “stacked” on top.
I/O Expander
As the M.2 M-key Stack FMC passes through all I/O (except gigabit transceivers) to the second mezzanine card, it has an I/O expander ( TI, IO Expander, TCA9536DTMR ) to allow the FPGA/MPSoC board to control each M.2 module’s reset signal (PERST_A# and PERST_B#) over the I2C bus. The I/O expander can also be used to read the PRSNT_M2C_L signal that indicates whether a second mezzanine card is present. An illustration of the I/O expander’s connections is provided in the I2C section. More detailed information regarding the use of the I/O expander can be found in the datasheet .
I2C address
The I/O expander can be accessed over the I2C bus using the address 0x41.
| A6 | A5 | A4 | A3 | A2 | A1 | A0 | Hexadecimal |
|---|---|---|---|---|---|---|---|
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0x41 |
I2C registers
The table below lists the registers of the I/O expanders.
| Address | Register | RW |
|---|---|---|
| 0x00 | Input port | R |
| 0x01 | Output port | RW |
| 0x02 | Polarity inversion | RW |
| 0x03 | Configuration | RW |
| 0x50 | Special function | RW |
For registers 0x00, 0x01, 0x02 and 0x03, the bits 0 to 3 refer to the expander’s IOs: P0, P1, P2 and P3.
I/Os
The I/O expanders have 4x GPIOs, labelled P0, P1, P2 and P3. On the M.2 M-key Stack FMC, these I/Os are connected as follows:
| Expander I/O pin | Bit mask | Connects to | Description |
|---|---|---|---|
| P0 | 0x01 | PERST_A# | M2 Slot 1 reset (active-low) |
| P1 | 0x02 | PERST_B# | M2 Slot 2 reset (active-low) |
| P2 | 0x04 | PRSNT_M2C_L | 2nd Mezzanine present |
| P3 | 0x08 | Not connected |
All of the I/O expander GPIOs default to inputs on power-up. The PERST_A# and PERST_B# signals are connected to pull-up resistors, to ensure that the M.2 modules are released from reset on power-up, even if the FPGA/MPSoC has not configured the I/O expander. Most applications can leave the I/O expander in it’s default configuration.