Programming Guide

This section provides the details of the programming requirements to operate the FPGA Drive FMC Gen4 hardware and customise functionality.

IBERT testing

The FPGA Drive FMC Gen4 comes with 2x M.2 loopback modules. These modules can be used to test the combined signal integrity of the carrier and mezzanine card, and can be useful when debugging issues on custom boards. To illustrate the use of the M.2 loopback modules with IBERT, we have put together the following videos.

Part 1: Hardware setup

How to attach the M.2 loopback modules and prepare your hardware for the IBERT loopback test.

Part 2: Using IBERT in Vivado

Download the pre-built IBERT bitstream:

Try this: disable the DFE (decision feedback equalizer) when doing a 2D eye scan – the gigabit traces on the FPGA Drive FMC have very low losses, so the performance is generally better without the DFE.

Part 3: Generate your own IBERT

How to generate an IBERT bitstream for your own hardware if you don’t find a pre-built bitstream listed above.

EEPROM

The 2K EEPROM is intended to store information that identifies the mezzanine card and also specifies the power supplies required by the card. This information is typically read by the system power management on the carrier board when it is powered up. In typical user applications, it should not be necessary to read the data on the EEPROM, and we highly recommend against writing to the EEPROM. Nevertheless, if you wish to access the EEPROM, it can be read and written to at the I2C address 0x50.

A6A5A4A3A2A1A0Hexadecimal
10100000x50

The FMC pins of the EEPROM’s I2C bus are shown below, and it is up to the user to determine their corresponding connections to the FPGA/MPSoC on the carrier board being used.

I2C bus signalFMC pin nameFMC pin number
SCL (clock)SCLC30
SDA (data)SDAC31

Restoring contents

If you need to reprogram the EEPROM with the original factory contents, you can use the Opsero FMC EEPROM Tool.