Guides on Opsero Docs

Getting Started

Mon, 23 Feb 2026 00:00:00 -0500

Minimum setup

To develop with the Ethernet FMC, we recommend you start by getting your hands on the minimum hardware and software requirements:

Programming Guide

Mon, 23 Feb 2026 00:00:00 -0500

This section provides the details of the programming requirements to operate the Ethernet FMC hardware and customise functionality.

PHY registers

For correct operation of the Ethernet FMC, the 4x Marvell Gigabit Ethernet PHYs must be properly configured over the MDIO bus (for more information, see PHY Configuration). The Marvell PHYs have registers that control the operation and functionality of the device and the Ethernet link. The registers have default values that are applied when the PHY is powered up and released from reset. The default register values are suitable for a wide range of use cases, but some of them you might want to change to suit your application.

RGMII Interface Timing Considerations

Mon, 23 Feb 2026 00:00:00 -0500

RGMII Timing Basics

The RGMII interface is the physical connection between the Ethernet PHY and the Ethernet MAC. If you are using the Ethernet FMC, the PHY is the Marvell 88E151x , and the Ethernet MAC is inside the FPGA. The RGMII interface is a dual data rate (DDR) interface that consists of a transmit path, from FPGA to PHY, and a receive path, from PHY to FPGA. Both paths have an independent clock, 4 data signals and a control signal.