Datasheet on Opsero Docs

Overview

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Description

The Ethernet FMC (FPGA Mezzanine Card) is an add-on/expansion board for FPGA and SoC based development boards. The mezzanine card has 4x Marvell 88E151x Gigabit Ethernet PHYs to provide 4 ports of gigabit Ethernet connectivity to the carrier development board.

Pin Configuration

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Pinout table

The Ethernet FMC has a low pin count FPGA Mezzanine Card (FMC) connector, providing the connections to the FPGA on the development board. The following table defines the pinout of the FMC connector and applies to both the Ethernet FMC and the Robust Ethernet FMC .

Specifications

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Recommended Operating Conditions

SUPPLY VOLTAGE	MIN	TYP	MAX	UNIT
12 VDC	+11.4	+12	+12.6	V
3.3 VDC	+3.14	+3.3	+3.46	V
VADJ 2.5VDC	+2.38	+2.5	+2.62	V
VADJ 1.8VDC	+1.71	+1.8	+1.89	V

Power Consumption

The specifications below refer to the total current draw on each of the power supplies while the Ethernet FMC is connected to a development board and operating at 100% channel utilization.

Detailed Description

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Hardware Overview

The figure below illustrates the various hardware components that are located on the top-side of the Ethernet FMC.

Mechanical Information

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Height Profile

The figure below illustrates the height profile of the Ethernet FMC. Note that the quad RJ45 connector with integrated magnetics has a maximum height of 13.84mm; this limits the Ethernet FMC for mating only with FMC connectors that are located close to the edge of the carrier board. In other words, the Ethernet FMC must be able to extend over the edge of the carrier board to allow for clearance of the RJ45 connector. All of the Xilinx development boards provide this level of clearance and are designed with the FMC connectors in close proximity to the edge of the board.

Compatible Boards

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This section of the documentation aims to list all of the development boards for which compatibility with the Ethernet FMC has been checked, and to list constraints and any notes concerning special requirements or limitations with the board.

Board Revision History

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Rev 1-1

Date of first manufacture: 2014-12-15
First board release
Supports VADJ 2.5V only

Rev B

Date of first manufacture: 2015-03-27
Increased via tenting diameters underneath QFNs to increase manufacturing yield
Optimizations to bottom layer planes
Added solder jumpers to REF_CLK_FSEL ¹ and REF_CLK_OE ² signals (see note ³).
125MHz oscillator VCC now connected to 3.3VDC

Rev C

Date of first manufacture: 2015-05-07
Increased via tenting diameters underneath QFNs to increase manufacturing yield
Removed “2V5” from silkscreen

Rev D

Date of first manufacture: 2015-07-16
R24, R25 changed to 240R 0402 to reduce part count
Via tenting under QFNs replaced by via-in-pad

Rev E

Date of first manufacture: 2016-05-02
Changed 125MHz oscillator to Micrel MEMS part DSC1123CI2-125.0000 to replace obsolete On Semi part NBXDPA019LNHTAG
Removed FSEL option - consequence of the oscillator part change
Added buffer to CLK_EN input to allow it to be driven at 1.8V
Removed the solder jumpers for FSEL and CLK_EN
Expanded FMC solder paste pads to improve manufacturing yield
Changed chassis filter capacitor to 1kV in 0805 package

Rev F

Date of first manufacture: 2020-02-04
JG0-0025NL Quad RJ45 footprint optimized to facilitate assembly
Added CE logo to silkscreen

REF_CLK_FSEL is an input of the clock oscillator and allows the output frequency to be set to either 125MHz or 250MHz. Floating this pin results in an output of 125MHz. ↩︎